![]() Furthermore, DSP Builder will generate a ModelSim testbench using the same vectors generated by Mathworks testbench, and also run the hardware verification. This allows for rapid design space exploration, enabling the designer to make trade-offs and ensure the design will fit into the chosen FPGA prior to invoking synthesis, fitting, and routing. DSP Builder will also provide resource estimations (e.g., logic, DSP blocks, memory) without the need to perform any FPGA compiles, which can be fairly time-consuming. The DSP Builder design can also be simulated within the Mathworks environment, thereby allowing full visibility and easy debug before any hardware is involved. Figure 12: Bit- and cycle-accurate Simulink simulation, automatic verification in RTL simulation, and 'System In The Loop' verification on connected hardware.
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